In a semiconductor device having a general high withstand voltage horizontal type MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a back gate electrode terminal and an electrode terminal for ground (ground electrode terminal) are electrically short-circuited through, for example, diffusion regions respectively constituting a channel forming region and a ground region, so that the back gate electrode terminal and the ground electrode terminal have the same electric potential (see, for example, Patent Literature 1).
In the above-described technology, however, there may be a case where applying a voltage to the back gate electrode-terminal different from the ground electrode terminal is desired. In such a case, it is necessary to form a back gate region and a ground region electrically isolated from each other. Consequently, there is proposed a semiconductor device having a high withstand voltage horizontal type MOSFET which has a back gate region and a ground region formed electrically isolated from each other (see, for example, Patent Literature 2).
The high withstand voltage horizontal type MOSFET comprises a P−-type semiconductor substrate, an N−-type semiconductor region formed on that substrate by epitaxial growth and functioning as a drain region, an upper P-type semiconductor region and a lower P-type semiconductor region both functioning as a ground region, a P-type semiconductor region which functions as a channel forming region, a first N+ semiconductor region formed in the N−-type semiconductor region and functioning as a drain contact region, a P+-type semiconductor region formed in the P-type semiconductor region and functioning as a back-gate contact region, and a second N+-type semiconductor region formed in the P-type semiconductor region and functioning as a source contact region.
The first N+ semiconductor region which functions as the drain contact region is formed in the surface region of the N−-type semiconductor region which functions as the drain region.
The P-type semiconductor region which functions as the channel forming region is formed in a closed ring shape so as to surround the first N+ semiconductor region.
The upper P-type semiconductor region is formed in a closed ring shape so as to surround the P-type semiconductor region. The lower P-type semiconductor region is so formed as to be adjacent to the bottom surface of the upper P-type semiconductor region.
The upper P-type semiconductor region is electrically connected to a ground electrode.
The P+-type semiconductor region which functions as the back-gate contact region is electrically connected to a back gate electrode.
The first N+ semiconductor region which functions as the drain contact region is electrically connected to a drain electrode.
The second N+ semiconductor region which functions as the source contact region is electrically connected to a source electrode.
A gate electrode is formed on the top surface of the P-type semiconductor region laid out between the second N+ semiconductor region which functions as the source contact region, and an the N−-type semiconductor region, though a gate insulating film
Patent Literature 1: Unexamined Japanese Patent Application KOKAI Publication No. 2000-260981
Patent Literature 2: Unexamined Japanese Patent Application KOKAI Publication No. H8-330580